1.Product Overview

CLM1543 is a 10 bit, 38kSPS ADC produced by Chiplon Microelectronics, with serial output, on-chip system clock, and 11 channel analog-to-digital converter. It adopts a serial communication interface and has the characteristics of multiple input channels, high cost-effectiveness, and easy interface with microcontrollers. It can be widely used in various data acquisition systems. CLM1543 is a CMOS 10 bit switched capacitor successive A/D approximation analog-to-digital converter. Among them, A0-A10 (pins 1-9, 11, and 12) are 11 analog inputs, REF+(pin 14, usually VCC) and REF - (pin 13, usually ground) are the reference voltage positive and negative terminals, CS (pin 15) is the chip selection terminal, and a falling edge change at the CS terminal will reset the internal counter and control and enable ADDRESS, I/O CLOCK (pin 18), and DATA OUT (pin 16).ADDRESS(17 pin) is the serial data input end, which is a 4-bit serial address used to select the next analog input or test voltage to be converted. DATA OUT is the 3-state serial output end of A/D conversion. It communicates with the microprocessor or the peripheral serial port, and the data length and format can be flexibly programmed. I/O CLOCK provides a synchronous clock for data input/output. The system clock is generated by the chip. There is a 14-channel multiplexer inside the chip, which can select any one of the 11 analog input channels or the 3 internal self-test voltages for testing. There is a sample-and-hold circuit inside the chip. At the end of the conversion, EOC(19 pin) output end becomes high to indicate the completion of the conversion. The internal converter has the characteristics of high speed (10μS conversion time), high precision (10-bit resolution, maximum ±1LSB unadjusted error) and low noise.

2.Working Sequence

The working process of CLM1543 is divided into two cycles: access cycle and sampling cycle. The working state is enabled or prohibited by CS, and CS must be set to low level when working. When CS is high level, I/O CLOCK and ADDRESS are prohibited, and DATA OUT is in high resistance state. When CPU makes CS low, CLM1543 starts data conversion, I/O CLOCK and ADDRESS are enabled, and DATA OUT is out of high resistance state. Then, CPU provides a 4-bit channel address to the ADDRESS end, and controls 14 analog channel selectors to select one path from 11 external analog inputs and 3 internal self-test voltages to the sampling hold circuit. At the same time, the clock timing is input by the I/O CLOCK end, and the CPU receives the previous A/D conversion result from the DATA OUT end.The I/O CLOCK receives a 10-clock-cycle clock sequence from the CPU. The first four clock cycles are used to load the address register with a 4-bit address from the ADDRESS pin, selecting the desired analog channel. The next six clock cycles provide the timing control for sampling the analog input. The sampling of the analog input starts at the falling edge of the fourth I/O CLOCK clock cycle and continues for six I/O CLOCK cycles. It is maintained until the falling edge of the tenth I/O CLOCK clock cycle. During the conversion process, the falling edge of the CS pin causes the DATA OUT pin to leave its high-impedance state and initiate a I/O CLOCK clock cycle. The rising edge of the CS pin terminates this process and returns the DATA OUT pin to its high-impedance state within the specified delay time. Two system clock cycles later, the I/O CLOCK and ADDRESS pins are disabled.

3.Key Points in Hardware and Software Design 

The three control inputs of CLM1543, CS, I/O CLOCK, ADDRESS, and the data output port DATA OUT, follow the Serial Peripheral Interface (SPI) protocol. Therefore, the microprocessor must have an SPI interface. However, most single-chip microcomputers do not have an SPI interface built-in (such as the widely used MCS51 and PIC series microcontrollers in China), so software simulation of the SPI protocol is required to interface with CLM1543. The three input ports and the output port of CLM1543 can be directly connected to the I/O ports of the 51 series microcontroller. In the software design, attention should be paid to distinguishing CLM1543's 11 analog input channels and 3 internal test voltage addresses.

4.Product features

10 bit resolution A/D converter

11 analog input channels

Three built-in self-test modes

Inherent sampling and holding functions

Unadjusted total error: maximum ± 1LSB

On-chip system clock

End of conversion (EOC) output

CMOS process

5.Application

Smart grid

New energy generation

Power system

Electrified railway tracks

Urban rail transit

Electric vehicle charging station

smart building